View CS8141_6441437.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2001 april, 2001 rev. 11 1 publication order number: cs8140/d cs8140, CS8141 5.0 v, 500 ma linear regulator with enable, reset , and watchdog the cs8140 and CS8141 are linear regulators suited for microprocessor applications in automotive environments. these on semiconductor parts provide the power for the microprocessors along with many of the control functions needed in today's computer based systems. incorporating all of these features saves both cost, and board space. packages are available for surface mounting as well as through hole mounting. the CS8141 has the same feature set as the cs8140 with the exception of the response to the watchdog signals (wdi). the CS8141 only responds to input signals (wdi) which are below the preset watchdog frequency threshold. features ? 5.0 v 4.0%, 500 ma output voltage ? m p compatible control functions watchdog reset enable ? low dropout voltage (1.25 v @ 500 ma) ? low quiescent current (7.0 ma @ 500 ma) ? low noise, low drift ? low current sleep mode (i q = 250 m a) ? fault protection thermal shutdown short circuit 60 v peak transient voltage ordering information http://onsemi.com see general marking information in the device marking section on page 13 of this data sheet. device marking information to220 seven lead t suffix case 821e 1 7 to220 seven lead tha suffix case 821h to220 seven lead tva suffix case 821j 1 7 1 d 2 pak 7pin dps suffix case 936h 1 7 device package shipping cs8140yt7 to220* straight 50 units/rail cs8140ytva7 to220* vertical cs8140ytha7 to220* horizontal cs8140ydps7 d 2 pak* CS8141yt7 CS8141ytva7 CS8141ytha7 750 tape & reel CS8141ydps7 d 2 pak* CS8141ydpsr7 d 2 pak* cs8140ydpsr7 d 2 pak* to220* straight to220* vertical to220* horizontal 50 units/rail 50 units/rail 50 units/rail 50 units/rail 50 units/rail 50 units/rail 50 units/rail 750 tape & reel *7lead/pin
cs8140, CS8141 http://onsemi.com 2 pin connections to220 seven lead d 2 pak seven pin 1 1 tab = gnd pin 1. v in 2. enable 3. reset 4. gnd 5. delay 6. wdi 7. v out tab = gnd pin 1. v in 2. enable 3. reset 4. gnd 5. delay 6. wdi 7. v out gnd reset v out figure 1. block diagram v in delay reference & bias enable wdi control logic enable reset delay watchdog regulation short circuit undervoltage overvoltage overtemperature absolute maximum ratings* rating value unit input operating range 0.5 to 26 v peak transient voltage (46 v load dump @ 14 v v bat ) 60 v electrostatic discharge (human body model) 4.0 kv wdi input signal range 0.3 to 7.0 v internal power dissipation internally limited junction temperature range (t j ) 40 to +150 c storage temperature range 65 to +150 c enable 0.3 to v in v lead temperature soldering: wave solder (through hole styles only) (note 1) reflow (smd styles only) (note 2) 260 peak 230 peak c 1. 10 second maximum. 2. 60 seconds max above 183 c. *the maximum package power dissipation must be observed.
cs8140, CS8141 http://onsemi.com 3 electrical characteristics (7.0 v in 26 v, 5.0 ma i out 500 ma, 40 c t j 150 c, 40 c t a 125 c, unless otherwise noted.) note 3 characteristic test conditions min typ max unit output stage (v out ) output voltage, v out 7.0 v v in 26 v, 5.0 ma < i out < 500 ma 4.8 5.0 5.2 v dropout voltage (v in v out ) i out = 500 ma 1.25 1.50 v line regulation i out = 50 ma, 7.0 v v in 26 v, 5.0 25 mv load regulation v in = 14 v, 50 ma i out 500 ma 5.0 80 mv output impedance, r out 500 ma dc and 10 ma ac, 100 hz f 10 khz 200 m w quiescent current, (i q ) active mode sleep mode 0 i out 500 ma, 7.0 v v in 26 v i out = 0 ma, v in = 13 v, enable = 0 v 7.0 0.25 15 0.50 ma ma ripple rejection 7.0 v v in 17 v, i out = 250 ma, f = 120 hz 60 75 db current limit 700 1200 2000 ma thermal shutdown 150 180 c overvoltage shutdown v out < 1.0 v 30 34 38 v enable threshold high low v out 0.5 v, (v out(on) ) v out < 0.5 v, (v out(off) ) 3.5 4.05 3.95 4.50 v v threshold hysteresis (high low) 100 mv reset threshold high v r(hi) v out increasing 4.65 4.90 v out 0.05 v threshold low v r(low) v out decreasing 4.50 4.70 4.90 v threshold hysteresis (v rh ) (high low) 150 200 250 mv reset output leakage reset = high v out v r(hi) 25 m a output voltage low (v l(low) ) 1.0 v v out v r(low) , r p = 2.7 k w, note 4 0.1 0.4 v output voltage low (v rpeak ) v out , power up, power down 0.6 1.0 v delay times t por c delay = 0.1 m f 30 47.5 65 ms delay times t wdi(reset ) c delay = 0.1 m f 0.5 1.0 1.5 ms watchdog input voltage high 2.0 v input voltage low 0.8 v input current wdi v out 0 10 m a threshold frequency f wdi(lower) c delay = 0.1 m f 64 77 96 hz threshold frequency f wdi(upper) (note 5.) c delay = 0.1 m f 218 262 326 hz 3. to observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable. 4. r p is connected to reset and v out. 5. cs8140 only.
cs8140, CS8141 http://onsemi.com 4 package lead description package lead # d 2 pak to220 lead symbol function 1 1 v in supply voltage to ic, usually direct from the battery. 2 2 enable cmos compatible logical input. v out is disabled when enable is low and wdi is beyond its preset limits. 3 3 reset cmos compatible output lead. reset goes low whenever v out drops below 4.5% of it's typical value for more than 2.0 m s or wdi signal falls outside it's win- dow limits. 4 4 gnd ground connection. 5 5 delay timing capacitor for watchdog and reset functions. 6 6 wdi cmos compatible input lead. the watchdog function monitors the falling edge of the incoming digital pulse train. the signal is usually generated by the system microprocessor. 7 7 v out regulated output voltage, 5.0 v (typ). typical performance characteristics v in (v) 012 34 6 8 10 5 figure 6. v out vs. v in over r load ; t = 25 c 3.0 2.5 2.0 1.5 1.0 0.5 0 v out (v) 9 figure 7. v out vs. v in over temperature; r load = 25 w v in ( v ) 012 3 4 5 3.0 2.5 0 v out (v) 2.0 1.5 1.0 0.5 v enable = v in temp = 40 c 3.5 temp = 125 c temp = 25 c 4.0 4.5 5.0 5.5 678910 figure 8. dropout voltage vs. output current over temperature figure 9. load regulation vs. output current over temperature 7 i out (ma) 0 100 200 300 400 600 800 500 800 600 400 200 0 dropout voltage (mv) 1000 1200 1400 1600 1800 700 i out (mv) 0 100 200 300 400 600 800 500 14 17.5 21 24.5 28 31.5 35 load regulation (mv) 10.5 7 3.5 0 3.5 700 v enable = v in r load = no load r load 10 w 3.5 4.0 4.5 5.0 5.5 125 c 40 c 25 c 40 c 125 c 25 c r load = 6.67 w v in = 14 v
cs8140, CS8141 http://onsemi.com 5 typical performance characteristics (continued) figure 10. line regulation vs. output current over temperature figure 11. quiescent current vs. output current over temperature i out (ma) 0 100 200 300 400 600 800 500 6 4 2 0 2 4 6 line regulation (mv) v in = 14 v 25 c 8 40 c 125 c 10 12 14 16 700 18 i out (ma) 0 100 200 300 400 600 800 500 5 4 i q (ma) v in = 14 v 25 c 6 40 c 125 c 7 8 9 700 10 v in (v) 08 12 7 34 18 14 12 8 16 10 0 i q (ma) 6 5 v in (v) i q (ma) figure 12. quiescent current vs. v in over r load ; t = 25 c t j ( c) 40 30 2010 010 180 140 120 100 80 60 f requency (h z ) 160 200 20 30 figure 13. quiescent current vs. v in over temperature; r load = 25 w figure 14. watchdog frequency thresholds vs. temperature figure 15. watchdog frequency threshold vs. c delay 2 4 6 20 08 12 7 34 18 14 12 8 16 10 0 6 5 2 4 6 20 220 240 40 capacitance (pf) 10 1 10 2 10 3 10 4 10 7 10 5 10 4 10 3 10 2 10 0 wdi threshold 10 6 10 1 910 v enable = v in r load = no load r load = 25 r load = 6.67 v enable = v in temp = 25 c temp = 125 c temp = 40 c 910 260 280 300 50 60 70 80 90 100 110 120 130 140 150 c delay = 0.1 m f lower threshold upper threshold 10 5 10 6 10 7 upper threshold lower threshold
cs8140, CS8141 http://onsemi.com 6 typical performance characteristics (continued) reset output current (ma) 1 5 10 25 30 40 1200 800 600 400 200 0 reset output voltage (mv) 1000 frequency (hz) 10 0 10 1 10 2 10 3 10 4 10 5 70 50 40 30 20 0 rejection (db) 60 10 6 10 7 10 8 10 80 90 figure 16. ripple rejection vs. frequency figure 17. reset output voltage vs. output current 1400 1600 1800 2000 15 20 35 c o = 10 m f, esr = 1.0 & 0.1 m f, esr = 0 c out = 10 m f, esr = 1.0 w c out = 10 m f, esr = 1.0 w i o = 250 ma v in = 5.0 v definition of terms dropout voltage: the inputoutput voltage differential at which the circuit ceases to regulate against further reduction in input voltage. measured when the output voltage has dropped 100 mv from the nominal value obtained at 14 v input, dropout voltage is dependent upon load current and junction temperature. input voltage: the dc voltage applied to the input terminals with respect to ground. line regulation: the change in output voltage for a change in the input voltage. the measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. load regulation: the change in output voltage for a change in load current at constant chip temperature. quiescent curr ent: the part of the positive input current that does not contribute to the positive load current. the regulator ground lead current. ripple rejection: the ratio of the peaktopeak input ripple voltage to the peaktopeak output ripple voltage. current limit: peak current that can be delivered to the output. circuit description the cs8140 is a 5.0 v watchdog regulator with protection circuitry and three logic control functions that allow a microprocessor to control its own power supply. the cs8140 is designed for use in automotive, switch mode power supply post regulator, and battery powered systems. basic regulator performance characteristics include a low noise, low drift, 5.0 v 4.0% precision output voltage with low dropout voltage (1.25 v @ i out = 500 ma) and low quiescent current (7.0 ma @ i out = 500 ma). on board short circuit, thermal, and overvoltage protection make it possible to use this regulator in particularly harsh operating environments. the watchdog logic function monitors an input signal (wdi) from the microprocessor or other signal source. when the signal frequency moves outside externally programmable window limits, a reset signal is generated (reset ). an external capacitor (c delay ) programs the watchdog window frequency limits as well as the power on reset (por) and reset delay. the reset function is activated by any of three conditions: the watchdog signal moves outside of its preset limits; the output voltage drops out of regulation by more than 4.5%; or the ic is in its power up sequence. the reset signal is independent of v in and reliable down to v out = 1.0 v. in conjunction with the w atchdog, the enable function controls the regulator's power consumption. the cs8140's output stage and its attendant circuitry are enabled by setting the enable lead high. the regulator goes into sleep mode when the enable lead goes low and the watchdog signal moves outside its preset window limits. this unique combination of control functions in the cs8140 gives the microprocessor control over its own power down sequence:
cs8140, CS8141 http://onsemi.com 7 i.e. it gives the microprocessor the flexibility to perform housekeeping functions before it powers down. the CS8141 has the same features as the cs8140, except that the CS8141 only responds to input signals (wdi) which are below the preset watchdog frequency threshold. voltage reference and output circuitry precision voltage reference the regulated output voltage depends on the precision band gap voltage reference in the ic. by adding an error amplifier into the feedback loop, the output voltage is maintained within 4.0% over temperature and supply variation. output stage the composite pnpnpn output structure (figure 18) provides 500 ma (min) of output current while maintaining a low drop out voltage (1.25 v) and drawing little quiescent current (7.0 ma). figure 18. composite output stage of the cs8140/1 v out v in the npn pass device prevents deep saturation of the output stage which in turn improves the ic's efficiency by preventing excess current from being used and dissipated by the ic. output stage protection the output stage is protected against overvoltage, short circuit and thermal runaway conditions (figure 19). if the input voltage rises above 30 v (e.g. load dump), the output shuts down. this response protects the internal circuitry and enables the ic to survive unexpected voltage transients. using an emitter sense scheme, the amount of current through the npn pass transistor is monitored. feedback circuitry insures that the output current never exceeds a preset limit. figure 19. typical circuit waveforms for output stage protection i o load dump v in v out thermal shutdown short circuit > 30 v should the junction temperature of the power device exceed 180 c (typ), the power transistor is turned off. thermal shutdown is an effective means to prevent die overheating since the power transistor is the principle heat source in the ic. regulator control functions the cs8140 differs from all other linear regulators in its unique combination of control features. watchdog and enable function v out is controlled by the logic functions enable and watchdog (table 1). table 1. v out as a function of enable and watchdog v out (v) wdi enable slow normal fast high low h 5 5 5 5 5 l 0 5 0 0 0
cs8140, CS8141 http://onsemi.com 8 v out when watchdog is held high and enable = high por normal operation wdi held high v in enable wdi reset v out 0 v 0 v 0 v batt batt por normal operation wdi held low v in enable wdi reset v out 0 v 0 v 0 v batt batt por normal operation slow wdi signal v in enable wdi reset v out 0 v 0 v 0 v batt batt por normal operation fast wdi signal v in enable wdi reset v out 0 v 0 v 0 v batt batt por normal operation sleep mode v in enable wdi reset v out 0 v 0 v 0 v batt batt wdi high por normal operation v out when watchdog is held low and enable = high v out when watchdog is too slow and enable = high v out when watchdog is too fast and enable = high wdi held high after a normal period of operation; enable = low wdi held low or is too slow after a normal period of operation; enable = low wdi frequency rises above the upper frequency threshold after a normal period of operation; enable = low (for cs8140 only) por normal operation sleep mode v in enable wdi reset v out 0 v 0 v 0 v batt batt wdi low por normal operation por normal operation sleep mode v in enable wdi reset v out 0 v 0 v 0 v batt batt por normal operation figure 20. timing diagrams for watchdog and enable functions
cs8140, CS8141 http://onsemi.com 9 as long as enable is high or enable is low and the watchdog signal is normal, v out will be at 5.0 v (typ). if enable is low and the watchdog signal moves outside programmable limits, the output transistor turns off and the ic goes into sleep mode. only the enable circuitry in the ic remains powered up, drawing a quiescent current of 250 m a. the watchdog monitors the frequency of an incoming wdi signal. if the signal falls outside of the wdi window, a frequency programmable pulse train is generated at the reset lead (figure 20) until the correct watchdog input signal reappears at the lead (enable = high). the lower and upper window threshold limits of the watchdog function are set by the value of c delay . the limits are determined according to the following equations for the cs8140: t wdi(lower) (1.3 10 5) c delay or f wdi(lower) (7.69 10 6 )c delay 1 t wdi(upper) (3.82 10 4 )c delay or f wdi(upper) (2.62 10 5 )c delay 1 (a) (b) for the CS8141 the lower limit is determined by the equations in (a) above. the capacitor c delay also determines the frequency of the reset signal and the poweronreset (por) delay period. reset function the reset function is activated when the watchdog signal is outside of its preset window (figure 20), when the regulator is in its power up state (figure 21) or when v out drops below v out 4.5% for more than 2.0 m s (figure 22) if the watchdog signal falls outside of the preset voltage and frequency window, a frequency programmable pulse train is generated at the reset lead (figure 20) until the correct watchdog input signal reappears at the lead. the duration of the reset pulse is determined by c delay according to the following equation: t wdi(reset ) (1.0 10 4) c delay reset circuit waveforms with delays indicated figure 21. power reset and power down v out reset v r(hi) v r(lo) v r(peak) v r(lo) t por figure 22. undervoltage triggered reset 5.0 v v out reset v out 4.5% < 2.0 m s t por 2.0 m s if an undervoltage condition exists, the voltage on the reset lead goes low and the delay capacitor, c delay , is discharged. reset remains low until output is in regulation, the voltage on c delay exceeds the upper switching threshold and the watchdog input signal is within its set window limits (figures 21 and 22). the delay after the output is in regulation is: t por(typ) (4.75 10 5) c delay the reset delay circuit is also programmed with the external cap c delay . the output of the reset circuit is an open collector npn. reset is operational down to v out = 1.0 v. both reset and its delay are governed by comparators with hysteresis to avoid undesirable oscillations.
cs8140, CS8141 http://onsemi.com 10 application notes cs8140 design example the cs8140 with its unique integration of linear regulator and control features: reset , enable and watchdog, provides a single ic solution for a microprocessor power supply. the reset delay, reset duration and watchdog frequency limits are all determined by a single capacitor. for a particular microprocessor the overriding requirement is usually the reset delay (also known as power on reset). the capacitor is chosen to meet this requirement and the reset duration and watchdog frequency follow. the reset delay is given by: t por(typ) (4.75 10 5) c delay assume that the reset delay must be 200 ms minimum. from the cs8140 data sheet the reset delay has a 37% tolerance due to the regulator. assume the capacitor tolerance is 10%. t por (min) (4.75 10 5 0.63) c delay 0.9 c delay (min) t por (min) 2.69 10 5 c delay (min) 0.743 f closest standard value is 0.82 m f. minimum and maximum delays using 0.82 m f are 220 ms and 586 ms. the duration of the reset pulse is given by: t wdi(reset ) (typ) (1.0 10 4) c delay this has a tolerance of 50% due to the ic, and 10% due to the capacitor. the duration of the reset pulse ranges from 3.69 ms to 13.5 ms. the watchdog signal can be expressed as a frequency or time. from a programmers point of view, time is more useful since they must ensure that a watchdog signal is issued consistently several times per second. the maximum and minimum watchdog times are given by: t wdi(lower) (1.3 10 5 )c delay t wdi(upper) (3.82 10 4 )c delay there is a tolerance of 20% due to the cs8140. with a capacitor tolerance of 10%: t wdi(lower) (1.3 10 5 ) 1.2 1.1 c delay t wdi(upper) (3.82 10 4 ) 0.8 0.9 c delay t wdi(lower) 141 ms (max) t wdi(upper) 22.5 ms (max) t wdi(lower) (1.3 10 5 ) 0.8 0.9 c delay t wdi(upper) (3.82 10 4 ) 1.2 1.1 c delay t wdi(lower) 76 ms (min) t wdi(upper) 41 ms (min) the software must be written so that a watchdog signal arrives at least every 76 ms but not faster than every 41 ms (figure 23). figure 23. wdi signal for c delay = 0.82 m f using cs8140 hz ms 7 fail fail pass 913 243244 141 107 76 41 31 22.5 c = 0.1 m f 10% the CS8141 is identical to the cs8140 except that the CS8141 only has a lower watchdog frequency threshold. the designer using this part need only be concerned with t wdi(lower) as shown in figure 24. figure 24. wdi signal for c delay = 0.82 m f using CS8141 hz ms 7 fail 13 141 76 pass energy conservation and smart features energy conservation is another benefit of using a regulator with integrated microprocessor control features. using the cs8140 or CS8141 as indicated in figure 25, the microprocessor can control its own power down sequence. the momentary contact switch quickly charges c1 through r1. when the voltage across c1 reaches 3.95 v ( the enable threshold), the output switches on and v out rises to 5.0 v. after a delay period determined by c delay , a frequency programmable reset pulse train is generated at the reset output. the pulse train continues until the correct watchdog signal appears at the wdi lead. c1 is now left to discharge through the input impedance of the enable lead (approximately 150 k w ) and the enable signal disappears. the output voltage remains at 5.0 v as long as the cs8140 continues to receive the correct watchdog signal.
cs8140, CS8141 http://onsemi.com 11 figure 25. application diagram for cs8140. the cs8140 provides a 5.0 v tightly regulated supply and control function to the microprocessor. in this application, the microprocessor controls its own power down sequence (see text). cs8140/1 wdi reset v out v in enable c delay gnd v cc reset watchdog port microprocessor c 1 0.1 m f 10 m f c 2 0.1 m f 2.7 k w r 1 110 k 9.0 v switch the microprocessor can power itself down by terminating its watchdog signal. when the microprocessor finishes its housekeeping or power down software routine, it stops sending a watchdog signal. in response, the regulator generates a reset signal and goes into a sleep mode where v out drops to 0 v, shutting down the microprocessor. stability considerations the output or compensation capacitor c 2 in figure 26 helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr can cause instability. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (25 c to 40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturers data sheet usually provides this information. the value for the output capacitor c 2 shown in figure 26 should work for most applications, however it is not necessarily the optimized solution. to determine an acceptable value for c 2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part.
cs8140, CS8141 http://onsemi.com 12 figure 26. application diagram cs8140 battery ignition wdi reset v out v in enable delay gnd c 1 * 0.1 m f (optional) 0.1 m f r*** c 2 * 10 m f* 2.7 k w v cc reset watchdog port microprocessor *c1 is required if regulator is located far from the power source filter. **c2 is required for stability. ***r 80 k w . step 1: place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. a decade box connected in series with the capacitor will simulate the higher esr of an aluminum capacitor. leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. step 2: with the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. if no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. step 3: increase the esr of the capacitor from zero using the decade box and vary the load current until oscillations appear. record the values of load current and esr that cause the greatest oscillation. this represents the worst case load conditions for the regulator at low temperature. step 4: maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. this point represents the worst case input voltage conditions. step 5: if the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. a smaller capacitor will usually cost less and occupy less board space. if the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next lar ger standard capacitor value. step 6: test the load transient response by switching in various loads at several frequencies to simulate its real working environment. vary the esr to reduce ringing. step 7: increase the temperature to the highest specified operating temperature. v ary the load current as instructed in step 5 to test for any oscillations. once the minimum capacitor value with the maximum esr is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. the esr of the capacitor should be less than 50% of the maximum allowable esr found in step 3 above. calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 27) is: p d(max) v in(max) v out(min) i out(max) v in(max) i q (1) where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current for the application, and i q is the quiescent current the regulator consumes at i out(max) . figure 27. single output regulator with key performance parameters labeled smart regulator ? control features i out i in i q v in v out once the value of p d(max) is known, the maximum permissible value of r q ja can be calculated: r ja 150 c t a p d (2)
cs8140, CS8141 http://onsemi.com 13 the value of r q ja can then be compared with those in the package section of the data sheet. those packages with r q ja 's less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. heat sinks a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r q ja . r ja r jc r cs r sa (3) where: r q jc = the junctiontocase thermal resistance, r q cs = the casetoheatsink thermal resistance, and r q sa = the heatsinktoambient thermal resistance. r q jc appears in the package section of the data sheet. like r q ja , it too is a function of package type. r q cs and r q sa are functions of the package type, heatsink and the interface between them. these values appear in heat sink data sheets of heat sink manufacturers. marking diagrams x = specific device code a = assembly location wl, l = wafer lot yy, y = year ww, w = work week to220 seven lead d 2 pak seven pin cs814x awlyww 1 cs814x awlyww 1
cs8140, CS8141 http://onsemi.com 14 package dimensions to220 seven lead t suffix case 821e04 issue c dim a min max min max millimeters 0.600 0.610 15.24 15.49 inches b 0.386 0.403 9.80 10.23 c 0.170 0.180 4.32 4.56 d 0.028 0.037 0.71 0.94 g 0.045 0.055 1.15 1.39 h j 0.018 0.026 0.46 0.66 k 1.028 1.042 26.11 26.47 l 0.355 0.365 9.02 9.27 m 5 nom q 0.142 0.148 3.61 3.75 u 0.490 0.501 12.45 12.72 v 0.045 0.055 1.15 1.39 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include dambar protrusion. allowable protrusion shall be 0.003 (0.076) total in excess of the d dimension at maximum material condition. 5 nom 0.088 0.102 2.24 2.59 a k u l q d g b c m m v m j h seating plane optional chamfer m to220 seven lead tha suffix case 821h02 issue a notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum. 1. leads maintain a right angle with respect to the package body to with 0.020". a u d g b t m 0.356 (0.014) m q 7 pl q k f j c e t n l m w s dim min max min max millimeters inches a 0.560 0.590 14.22 14.99 b 0.385 0.415 9.77 10.54 c 0.160 0.190 4.06 4.82 d 0.023 0.037 0.58 0.94 e 0.045 0.055 1.14 1.40 f 0.568 0.583 14.43 14.81 g 0.050 bsc 1.27 bsc j 0.015 0.022 0.38 0.56 k 0.728 0.743 18.49 18.87 l 0.322 0.337 8.18 8.56 m 0.101 0.116 2.57 2.95 n 0.090 0.115 2.28 2.91 q 0.146 0.156 3.70 3.95 s 0.150 0.200 3.81 5.08 u 0.460 0.475 11.68 12.07 w 33
cs8140, CS8141 http://onsemi.com 15 to220 seven lead tva suffix case 821j02 issue a d 2 pak 7pin dps suffix case 936h01 issue o t dim min max min max millimeters inches a 0.326 0.336 8.28 8.53 b 0.396 0.406 10.05 10.31 c 0.170 0.180 4.31 4.57 d 0.026 0.036 0.66 0.91 e 0.045 0.055 1.14 1.40 f 0.058 0.078 1.41 1.98 g 0.050 bsc 1.27 bsc h 0.100 0.110 2.54 2.79 j 0.018 0.025 0.46 0.64 k 0.204 0.214 5.18 5.44 m 0.055 0.066 1.40 1.68 n 0.000 0.004 0.00 0.10 notes: 1. dimensions and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. tab contour optional within dimensions b and m. 4. dimensions a and b do not include mold flash or gate protrusions. mold flash and gate protrusions not to exceed 0.025 (0.635) max. b n a k m e c seating plane f h j d 7 pl g t m 0.13 (0.005) m b 12345 u 0.256 ref 6.50 ref v 0.305 ref 7.75 ref 67 8 u v notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum. a u d g b t m 0.356 (0.014) m q 7 pl q k f j c e t n l m w dim min max min max millimeters inches a 0.560 0.590 14.22 14.99 b 0.385 0.415 9.77 10.54 c 0.160 0.190 4.06 4.82 d 0.023 0.037 0.58 0.94 e 0.045 0.055 1.14 1.40 f 0.540 0.555 13.72 14.10 g 0.050 bsc 1.27 bsc j 0.014 0.022 0.36 0.56 k 0.785 0.800 19.94 20.32 l 0.322 0.337 8.18 8.56 m 0.073 0.088 1.85 2.24 n 0.090 0.115 2.28 2.91 q 0.146 0.156 3.70 3.95 s 0.164 0.179 4.17 4.55 u 0.460 0.475 11.68 12.07 w 33 r s h h 14.48 15.11 0.570 0.595 r 0.289 0.304 7.34 7.72
cs8140, CS8141 http://onsemi.com 16 package thermal data parameter to220 seven lead d 2 pak seven pin unit r q jc typical 1.6 1.5 c/w r q ja typical 50 1050* c/w *depending on thermal properties of substrate r q ja = r q jc + r q ca.
cs8140, CS8141 http://onsemi.com 17 notes
cs8140, CS8141 http://onsemi.com 18 notes
cs8140, CS8141 http://onsemi.com 19 notes
cs8140, CS8141 http://onsemi.com 20 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 13036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. cs8140/d smart regulator is a registered trademark of semiconductor components industries, llc (scillc). north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

▲Up To Search▲

Price & Availability of CS8141

	To Download CS8141 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .